AiEDA

Open-Source EDA & AI-Driven Chip Design

Southeast University (SEU) & Chinese University of Hong Kong (CUHK)
We develop open-source EDA infrastructure and AI-aided design tools that push the frontier of intelligent chip design automation.

80+
Publications
3
ICCAD 1st-Place Awards
21
Patents Filed
10+
Open-Source Projects
10+
Team Members

Research Directions

Open-Source EDA

Leading development of iEDA – a complete open-source physical implementation toolchain covering floorplan, placement, clock tree synthesis, routing, timing, and DRC.

AI for EDA (AI4EDA)

Building the AiEDA library and iDATA vector dataset. Machine learning models for placement, routing, timing prediction, logic optimization, and design rule checking.

Large Circuit Models

Pre-training foundation models (iPCL) on chip layout data to enable zero-intervention layout generation and cross-stage design optimization.

AI for Algorithm Design (AI4AD)

Applying reinforcement learning, graph neural networks, and transformer architectures to combinatorial optimization problems in EDA and beyond.

Photonic Design Automation (PDA)

Extending EDA principles to photonic integrated circuits, exploring AI-driven design flows for next-generation optical computing devices.

LLM for EDA

Leveraging large language models to automate RTL generation, EDA scripting, design space exploration, and natural-language-driven chip design flows.

Featured Projects

iEDA

iEDA

Open-Source Intelligent Physical Implementation Toolchain

A complete EDA infrastructure for placement, routing, CTS, timing optimization, and DRC – built for research and industry use.

Key Features:

  • Full physical design flow (FP → PL → CTS → RT → STA → DRC)
  • Modular, extensible C++ architecture
  • Best Paper Award at ISEDA 2023
  • Active open-source community
AiEDA

AiEDA

AI-Aided Design Library for Design-to-Vector

An open-source AI library bridging chip design and machine learning – from feature extraction and vector datasets to trained models and benchmark evaluation.

Key Features:

  • Design-to-vector conversion pipeline
  • iDATA: standardized EDA dataset
  • Pretrained models for EDA tasks
  • Published in IEEE TCAD 2025 (CCF-A)
iPCL

iPCL

Pre-training for Chip Layout – Large Layout Model

Foundation model pre-trained on large-scale chip layout data. Enables layout generation and metric evaluation without manual intervention or EDA tool execution.

Key Features:

  • Self-supervised layout pre-training
  • Zero-intervention layout generation
  • Metric evaluation & optimization (iPCL-M)
  • Accepted at DAC 2026 (CCF-A)
View All Projects

Recent News

Mar 2026 Paper AiEDA: An Open-Source AI-Aided Design Library for Design-to-Vector accepted in IEEE TCAD 2025 (CCF-A).
Feb 2026 Paper iPCL-M and DiffDEG accepted at DAC 2026 (CCF-A).
Jan 2026 Paper iPCL: Pre-training for Chip Layout presented at ASP-DAC 2026.
Jun 2025 Paper Clock Skew Scheduling and Routability-Driven Global Placement accepted at DAC 2025 (CCF-A).
Nov 2024 Paper NeuralSteiner accepted at NeurIPS 2024 (CCF-A).
Jun 2024 Paper Two papers accepted at DAC 2024 (CCF-A): CTS and Net Resource Allocation.
May 2023 Award iEDA receives Best Paper Award at ISEDA 2023.
View All News

Selected Publications

Google Scholar Full Publication List (70+ papers)

2026

CircuitFlow: Learning Dynamic Representations for Logic Optimization

Miao Liu, Xinhua Lai, Liwei Ni, Xingyu Meng, Rui Wang, Junfeng Liu, Xingquan Li, Jungang Xu

IEEE TCAD, 2026 (CCF-A)

2026

iPCL-M: Pre-training of Chip Layout for Metrics Evaluation and Optimization

Xinhua Lai, He Liu, Weiguo Li, Yihang Qiu, Miao Liu, Simin Tao, Xingquan Li, Jungang Xu

DAC, 2026 (CCF-A)

2025

AiEDA: An Open-Source AI-Aided Design Library for Design-to-Vector

Yihang Qiu, Zengrong Huang, Simin Tao, Hongda Zhang, Weiguo Li, Xinhua Lai, Rui Wang, Weiqiang Wang, Xingquan Li

IEEE TCAD, 2025 (CCF-A)

2025

iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree

Weiguo Li, Zhipeng Huang, Bei Yu, Wenxing Zhu, Jian Chen, Zhixue He, Xingquan Li

IEEE TCAD, 2025 (CCF-A)

2024

NeuralSteiner: Learning Steiner Tree for Overflow-avoiding Global Routing in Chip Design

Ruizhi Liu, Zhisheng Zeng, Shizhe Ding, Jingyan Sui, Xingquan Li, Dongbo Bu

NeurIPS, 2024 (CCF-A)

2023

iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Library

Xingquan Li et al.

ISEDA, 2023 (Best Paper Award)

View All Publications

Open Source & Datasets

Our code, models, and datasets are publicly available. We welcome contributions and collaborations from the community.

Contact & Collaboration

Principal Investigator

Xingquan Li (李兴权), Associate Professor
Southeast University (SEU) & Chinese University of Hong Kong (CUHK)

Location

Room 401, Chuangzhi Building B, No. 17 Xinghuo Road, Pukou District, Nanjing, China