Projects

Open-Source Intelligent Physical Implementation Toolchain

A complete, modular EDA infrastructure covering the full physical design flow: floorplan → placement → clock tree synthesis → routing → static timing analysis → DRC/LVS.

AI-Aided Design Library for Design-to-Vector

Open-source AI library for EDA: feature extraction from chip designs, vector dataset construction (iDATA), pretrained ML models for placement, routing, timing, logic synthesis, and DRC tasks.

Pre-training for Chip Layout – Large Layout Model

Foundation model pre-trained on large-scale chip layout datasets. Enables zero-intervention layout generation, metric evaluation (iPCL-M), and cross-stage optimization without running traditional EDA tools.

Large Language Models for EDA Automation

Exploring LLM-based workflows for RTL generation, EDA scripting, design space exploration, and natural-language-driven chip design. Includes benchmark construction and evaluation frameworks.

EDA Flow Integration Framework

Docker-based EDA flow runner that integrates iEDA and other open-source EDA tools into end-to-end chip design flows. Enables reproducible experiments and CI/CD for EDA research.

AI-Driven Design Rule Checking

Accelerates detailed routing by AI-driven prediction and checking of design rule violations. Reduces DRC iterations and improves routing quality using deep learning on layout features.